Non volatile memory devices (e.g. electrically erasable programmable read only memory (EEPROM)) typically use floating gate metal oxide semiconductor technology to store data. Each memory cell contains a floating gate MOS transistor. A logical state is written into the memory cell by providing a required voltage between the substrate, source, gate and drain of the floating gate MOS transistor in order to cause tunneling of electrons (Fowler-Nordheim tunnelling) from the substrate through the floating gate oxide insulator onto the floating gate. The other logical state is written by providing specific voltages between the source, gate and drain which discharge electrons from the floating gate of the memory cell by tunneling electrons through the floating gate oxide insulator layer (sometimes known as the tunnel oxide) from the floating gate to the substrate. A capacitive structure within the memory cell, comprising the floating gate, control gate and dielectric, store charges and of the presence/absence of a charge determines the value (1 or 0) of the memory cell.
FIG. 1(a) is a cross-sectional diagram, designated generally as reference numeral 100, of a typical prior art non-volatile memory (NVM) cell, such as an electrically erasable programmable read only memory (EEPROM). The cell comprises a control gate 102, a floating gate 104 and a substrate layer 106. An n+ source 108 and an n+ drain 110 are disposed in the p-type substrate layer 106. The floating gate 104 is disposed above the substrate layer 106 and comprises a stacked silicon dioxide (gate oxide) layer 111, poly layer 112, contact 114 and metal pad 116. The poly layer 112 is disposed above the silicon dioxide layer 111 while the contact 114 is disposed above the poly layer 112 and below the metal layer 116. The metal pad 116 is typically made of aluminium. The control gate 102 is formed in the same metal layer and is disposed around the metal pad 116 to form a “ring” around the metal pad 116. A dielectric 118 is disposed above the substrate layer 106 and fills the space between the control gate 102 and the floating gate 104.
FIG. 1(b) is a perspective view, designated generally as reference numeral 150, of the typical prior art non-volatile memory (NVM) cell described above.
FIGS. 2(a)-(e) are schematic cross-sectional diagrams illustrating the fabrication process of the metal pad 116 and control gate 102 of the typical prior art non-volatile memory (NVM) cell described above. In FIG. 2(a), a metal layer 202, made from a suitable metal such as aluminium, is deposited. The aluminium is typically deposited through a sputtering process (physical vapour deposition (PVD)). In FIG. 2(b), a photoresist 204 is patterned over the metal layer 202. In FIG. 2(c), the metal layer 202 is selectively etched such that the portions of the metal layer 202a/b underlying the photoresist remain. In FIG. 2(d), a dielectric layer 206 is deposited over the remaining portions of the metal layer 202a/b. The dielectric layer 206 is usually made from silicon dioxide. In FIG. 2(e), a suitable process such as chemical-mechanical polishing is used to planarize the dielectric layer 206; the metal layer 202a corresponds to the left portion of the control gate 102a while the metal layer 202b corresponds to the metal layer 116. The right portion of the control gate is not shown in FIG. 2(e). As will be appreciated, the metal layer formation is thus typically a low aspect ratio process.
With reference to FIG. 1(b), typical prior art non-volatile memory (NVM) cells make use of the capacitance between the metal control gate and the metal floating gate. In other words, the area of overlap between the control gate 102 “ring” and the metal pad 116 of the floating gate 104 form the non-volatile memory cell's coupling capacitor. However, memory cells with this structure are relatively larger and provide limited capacitor area, due to the low aspect ratio of the metal layer-formed gates. Herein, aspect ratio is defined as the ratio between the depth and the width of a structure.
Furthermore, the area of overlap between the control gate and the metal layer of the floating gate in a typical prior art non-volatile memory cell is relatively small, consequently resulting in relatively lower capacitance and hence a larger voltage is require to program the non-volatile memory cell.
A need therefore exists to provide non-volatile memory cell structure and a method of fabricating the same that seeks to address at least one of the abovementioned problems.